High k gate stack on III-V compound semiconductors

ABSTRACT

A method of forming a high k gate stack (dielectric constant of greater than that of silicon dioxide) on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface of the III-V compound semiconductor material; forming a semiconductor, e.g., amorphous Si, layer in-situ on the cleaned surface of the III-V compound semiconductor material; and forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the semiconducting layer. In some embodiments, the semiconducting layer is partially or completely converted into a layer including at least a surface layer that is comprised of AO x N y  prior to forming the dielectric material. In accordance with the present invention, A is a semiconducting material, preferably Si, x is 0 to 1, y is 0 to 1 and x and y are both not zero.

FIELD OF THE INVENTION

The present invention relates to a semiconductor structure, and moreparticularly to a semiconductor structure including a dielectricmaterial having a dielectric constant of greater than that of silicondioxide located on a passivated surface of a III-V compoundsemiconductor in which the passivated surface has electrical propertiesthat are sufficient for high-performance field effect transistor (FET)applications. The present invention also provides a method offabricating such a semiconductor structure.

BACKGROUND OF THE INVENTION

In semiconductor technology, an elemental semiconductor material suchas, for example, Si or Ge, is typically used as a substrate in which oneor more semiconductor devices including, but not limited to, FETs andcapacitors, are formed. Of the various elemental semiconductormaterials, Si is the elemental semiconductor of choice due to processand performance benefits that are achieved using such an elementalsemiconductor material.

Alternative semiconductor materials such as, for example, compoundsemiconductors, are also known which are used for specific marketapplications. A major class of compound semiconductors are comprised ofat least one element from Group IIIA and Group VA of the Periodic Tableof Elements. Such compound semiconductors including an element fromGroup IIIA and VA are often referred to as III-V or III/V compoundsemiconductors. Illustrative examples of III-V compound semiconductorsinclude, but are not limited to: GaAs, InP, InAs, GaP, InSb, GaSb andGaN.

The need for alternative semiconductor materials is driven by the growthof markets that require integrated circuit (IC) performance beyond thatwhich Si semiconductors can provide. One key IC performance factor thatneeds to be achieved is high operating speeds. Wireless and high-speeddigital communications, space applications, and consumer markets aredeveloping special niche semiconductor markets that are centered on highspeed that can support higher signal frequencies.

GaAs, which is the most common III-V compound semiconductor material,has greater electron mobility than Si so the majority carriers movefaster than in Si. There are also some attributes of a GaAssemiconductor material that reduce parasitic capacitance and signalloses. These result in ICs that are generally faster than those madewith silicon. The improved signal speed of GaAs devices permits them toreact to high-frequency microwave signals and accurately converts theminto electrical signals. As such, products for wireless and high-speeddigital communications and high-speed optoelectronic devices are madefrom GaAs and other III-V compound semiconductors.

One major disadvantage of a GaAs semiconductor material (as well as theother III-V compound semiconductors) is the lack of a natural oxide.This feature hinders the development of standard metal oxidesemiconductor (MOS) devices that require the ability to form a surfacedielectric. Moreover, when a dielectric material having a dielectricconstant that is greater than silicon dioxide (k greater than 4.0) isdeposited on a GaAs semiconductor material that has an unpassivatedsurface, the interface between the high k dielectric and the GaAssemiconductor material is typically poor, resulting in a high interfacestate density (on the order of about 10¹³ cm⁻² eV⁻¹ or greater). Becauseof such a high interface state density, the electrical properties of thedielectric are insufficient for use with high-performance FETs.

Several known solutions have been proposed, but each haveproblems/drawbacks associated therewith. One such solution is disclosed,for example by Passlack et al. “Low D_(it), Thermodynamically StableGa₂O₃—GaAs Interfaces: Fabrication, Characterization, and Modeling”,IEEE Transactions on Electron Devices, Vol 44, No. 2, p. 214, February1997 and by M. Hong et al., “Low Interface State Density Oxide-GaAsStructures Fabricated by in situ Molecular Beam Epitaxy”, J. Vac. Sci.,Technol. B 14(3), p. 2297, May/June 1996. The prior art techniquedescribed in the two aforementioned disclosures involves deposition of aGa₂O₃/Gd₂O₅ oxide on a clean/reconstructed GaAs surface in an ultra-highvacuum using an ultra-low oxygen ambient. This prior art technique hasbeen shown to be successful in unpinning the GaAs/oxide interface, andproduces a very low density of interface states. However, it requires acomplex dual chamber molecular beam epitaxial (MBE) system which is notsuitable for manufacturing. Moreover, Ga₂O₃ has the problem that it hasa relatively low bandgap, and therefore can produce higher leakage thanis desirable for scaled MOSFET applications.

Another solution to the general problem mentioned above is disclosed,for example, in Tiwari et al. “Unpinned GaAs MOS Capacitors andTransistors”, IEEE Electron Device Letters, Vol. 9, No. 9, p. 488,September 1988; D. S. L. Mui et al, “Si₃N₄/Si/In_(0.53)Ga_(0.47)AsDepletion-mode Metal-Insulator-Semiconductor Field Effect TransistorsWith Improved Stability”, Appl. Phys. Lett., 62 (25), p. 3291, Jun. 21,1993; Z. Wang et al., “Si₃N₄/Si/n-GaAs Capacitor with Minimum InterfaceDensity in the 10¹⁰ eV⁻¹ cm⁻² Range”, Appl. Phys. Lett., 62 (23), p.2977, Jun. 7, 1993; Z. Wang et al., “Gate QualitySi₃N₄/Si/n-In_(0.53)Ga_(0.47)As Metal-Insulator-SemiconductorCapacitors”, Appl. Phys. Lett., 61 (15) p. 1826, Oct. 12, 1992; D. S. L.Mui et al. “Investigations of the Si₃N₄/Si/n-GaAsInsulator-Semiconductor Interface With Low Interface Trap Density”,Appl. Phys. Lett., 60 (20), p. 2511, May 18, 1992; and D. S. L. Mui etal. “Electrical Characteristics of Si₃N₄/Si/GaAsMetal-Insulator-Semiconductor Capacitor”, Appl. Phys. Lett. 59 (22), p.2847, Nov. 25, 1991. Specifically, each of the aforesaid articlesdisclose the deposition of a thin Si layer on top of a GaAs substrate ina MBE chamber after GaAs growth. In some of these disclosures, the Si isdeposited in the same chamber as the GaAs using a heated elemental Sisource. In other disclosures, a second dual chamber system is employed,and the interfacial Si is deposited using an ECR source, which allowshigher deposition rates. Both of these techniques mentioned in the abovearticles have the problem that an III-V MBE chamber is needed to firstproduce a high-quality GaAs interface before Si deposition.

Callegari et al., “Properties of SiO₂/Si/GaAs Structures Formed By SolidPhase Epitaxy of amorphous Si on GaAs”, App. Phys. Lett. 58, (22), p.2540, Jun. 3, 1991 provide a method wherein the GaAs compoundsemiconductor is subjected to a H-precleaning process prior todeposition, e.g., plasma enhanced chemical vapor deposition (PECVD) of aSi layer. After deposition of the Si layer, SiO₂ is formed on theprecleaned GaAs surface.

In addition to the above-mentioned techniques, several techniques havebeen purposed to passivate a GaAs surface, yet these techniques have notbeen utilized in conjunction with a high k dielectric. These prior artGaAs passivation techniques include, for example, nitrogen passivationand sulfur passivation. Both of the aforementioned passivationtechniques have been shown to unpin the GaAs surface under certainconditions, but it is not clear whether or not such passivationtechniques would work in conjunction with a high k dielectric.

In view of the above, there is a need for providing a method in which ahigh k dielectric stack can be formed on a surface of a III-V compoundsemiconductor material with electrical properties sufficient forhigh-performance FET applications. That is, a method is needed in whichthe interface between the high k dielectric stack and the III-V compoundsemiconductor material is of good quality, resulting in low interfacestate density (on the order of about 10¹² cm⁻² eV⁻¹ or less). Morespecifically, a structure including an unpinned III-V compoundsemiconductor surface is needed.

SUMMARY OF THE INVENTION

The present invention provides a method in which a high k dielectricmaterial having a dielectric constant of greater than that of silicondioxide can be formed on a surface of a III-V compound semiconductormaterial with electrical properties sufficient for high-performance FETapplications wherein the interface between the high k dielectricmaterial and the III-V compound semiconductor material is of goodquality, resulting in a low interface state density (on the order ofabout 10¹² cm⁻² eV⁻¹ or less); the unit for the interface state densitycan also be written as cm⁻²/eV. That is, the present invention providesa method in which a high k dielectric material is formed on an unpinned,i.e. passivated, surface of a III-V compound semiconductor material. Inaccordance with the method of the present invention, the surface of theIII-V compound semiconductor includes substantially no oxide or othercontaminants that would otherwise cause a large interface state densityin the structure.

In accordance with the present invention, the method begins by firstsubjecting a III-V compound semiconductor material to a cleaning stepthat is capable of removing any native oxides such as, Ga₂O₃ or As₂O₅,from the surface of the III-V compound semiconductor material. This stepprovides a treated surface that typically remains unpinned. The precleanmay be performed by a desorption process or, preferably, by a H plasmaprocess. A semiconducting layer (either amorphous or crystalline) isformed in-situ on the treated surface of the III-V compoundsemiconductor material. This step, together with the previousprecleaning step, provides a structure in which the surface of the III-Vcompound is passivated. Preferably, the semiconducting layer comprisesSi, with amorphous Si being even more highly preferred. At this point ofthe present invention, the semiconducting layer can optionally besubjected to a nitridation, oxidation or oxynitridation process. Thatis, the semiconducting layer is optionally converted, completely orpartially, into a layer or surface region that is comprised ofAO_(x)N_(y) wherein A is a semiconducting material, preferably Si, x isfrom 0 to 1 and y is from 0 to 1; note x and y can not both be zero atthe same time. In accordance with the present invention, an in-situ orex-situ oxidation, nitridation or oxynitridation process can be used.Next, a dielectric material (or multilayers thereof) that has adielectric constant that is greater than silicon dioxide is formed oneither the semiconducting layer, or the AO_(x)N_(y) layer.

In general terms, the method of present invention comprises:

-   removing native oxides from a III-V compound semiconductor material    to provide a treated surface;-   forming a semiconducting layer in-situ on said treated surface of    said III-V compound semiconductor material; and-   forming a dielectric material having a dielectric constant that is    greater than silicon dioxide on said semiconducting layer.

In one embodiment of the present invention, the method of presentinvention comprises:

-   removing native oxides from a III-V compound semiconductor material    to provide a treated surface;-   forming a semiconducting layer in-situ on said treated surface of    said III-V compound semiconductor material;-   converting at least an upper surface region of said semiconducting    layer to a region comprised of AO_(x)N_(y) wherein A is a    semiconducting material, x is from 0 to 1, y is from 0 to 1 and x    and y are not both 0; and-   forming a dielectric material having a dielectric constant that is    greater than silicon dioxide on the upper surface region of said    semiconducting layer.

In accordance with the present invention, the converting step mayinclude a complete or partial oxidation, nitridation or oxynitridationprocess. When complete conversion is achieved, the semiconductor layeris modified to comprise a AO_(x)N_(y) layer, wherein A, x and y are asdefined above. In a preferred embodiment, the semiconducting layer is Siwhich is modified to a SiO_(x)N_(y) layer. In this particularembodiment, the high k dielectric material is formed on a completelymodified semiconducting, e.g., SiO_(x)N_(y), layer. When partialconversion is achieved, an upper surface region of the originally formedsemiconducting layer is modified to include a AO_(x)N_(y) surface layerthat is located above the remaining semiconducting layer. In thisparticular embodiment, the dielectric material is formed on theconverted upper surface region of the semiconducting layer.

In a highly preferred embodiment of the present invention, the methodincludes the steps of:

-   subjecting a GaAs compound semiconductor material to a H preclean,    said H preclean removes native oxides from a surface of said GaAs    compound semiconductor material;-   forming an amorphous Si layer in-situ on said surface of said GaAs    compound semiconductor material;-   subjecting said Si layer to a nitridation process to form a silicon    nitride layer; and-   forming a Hf-based dielectric on said silicon nitride layer.

The methods of the present invention described above have has severaladvantages. First the semiconducting, e.g., Si, layer is excellent atpassivating a surface of a III-V compound semiconductor material,particularly a GaAs surface. Secondly, by depositing the semiconductinglayer using a high-quality technique such as MBE, the surface can becleaned (either by desorbing the oxygen at high temperatures, or using aH-plasma preclean), to create a virtually oxygen-free interface. Thesemiconducting layer thickness can be controlled to high precision aswell, and thus be made very thin. If the semiconducting layer isnitridated, in situ, a nitrogen plasma could be used to then convert thesemiconducting layer to a semiconducting nitride. Nitride, instead ofoxide, formation has the advantage that over nitridation will not causeproblems, as generally, nitridation of the GaAs surface does not degradethe electrical characteristics. Over oxidation, on the other hand, canseverely degrade the electrical characteristics. Once the nitride isformed, the surface is stable against oxidation, and could be removedand exposed to air, for subsequent high k deposition. A semiconductingnitride also has the advantage of allowing the subsequent HfO₂ that isdeposited to nucleate amorphous as opposed to polycrystalline, which canimprove the electrical properties. The HfO₂ could be deposited in situas well, which would have the advantage that the entire gate stack couldbe deposited in a single vacuum step. The inventive process has theadditional advantage that it does not require a high-temperature step,as the H-preclean, semiconducting layer deposition, optionalnitridation, oxidation or oxynitridation and high k deposition all couldbe performed at a temperature of less than 300° C., which would avoidany contamination or surface degradation problems associated withsublimation of one of the elements of the III-V compound semiconductormaterial.

In addition to the general method and other embodiments thereofdescribed above, the present invention also relates to a semiconductorstructure which includes a dielectric material located on a passivatedsurface of a III-V compound semiconductor material. In accordance withthis aspect of the present invention, the inventive structure generallyincludes:

-   a III-V compound semiconductor material having a surface that is    essentially free of oxides;-   a semiconducting layer located on said surface, wherein an interface    is present between the III-V compound semiconductor material and the    semiconducting layer that has an interface state density of about    10¹² cm⁻² eV⁻¹ or less; and-   a dielectric material having a dielectric constant greater than that    of silicon dioxide located on said semiconducting layer.

In some embodiments, the semiconducting layer includes at least asurface region of AO_(x)N_(y), where A, x and y are as defined above. Insuch an embodiment, the dielectric material is located on said surfaceregion of AO_(x)N_(y).

In yet another embodiment of the present invention, the semiconductinglayer of the inventive semiconductor structure is replaced by aAO_(x)N_(y) layer and the dielectric material is located on thatreplacement layer.

In a highly preferred embodiment, the semiconductor structure comprises:

-   a GaAs compound semiconductor material having a surface that is    essentially free of oxides;-   a silicon nitride layer located on said surface, wherein an    interface is present between GaAs and the silicon nitride layer that    has an interface state density of about 10¹² cm⁻² eV⁻¹ or less; and-   a Hf-based dielectric material located on said silicon nitride    layer.

In addition to the above, the applicants have determined that thepresence of the semiconducting layer acts as a robust cap during theactivation of implanted source/drain regions. There is no measurablesurface erosion observed in the inventive capped structure even afterannealing at temperatures of greater than 800° C. This cap is farsuperior to conventional caps of SiN_(x) or SiO_(X) where measurablesurface erosion occurs after annealing at 800° C. or greater.Accordingly, the present invention provides a method of enhancing theactivation of implanted dopants within a III/V compound semiconductormaterial that includes:

-   providing a semiconducting cap layer atop a III/V compound    semiconductor that has a surface that is essentially free of oxides,    said III/V compound semiconductor including n-type dopants and/or    p-type dopants; and-   annealing (typically at 800° C. or greater) the dopants to provide    at least one activated dopant region in said III/V compound    semiconductor.

In this particular embodiment of the present invention, the n-typedopants for III/V materials include Si, Ge, an element from Group VIA ofthe Periodic Table of Elements or any combination thereof, while thep-type dopants include C, an element from Group IIA of the PeriodicTable of Elements or any combination thereof. A conventional ionimplantation process, gas phase doping or plasma immersion process canbe used to introduce the dopants into the III/V compound semiconductormaterial and the annealing step is performed utilizing conventionalconditions that are well-known in the art.

It should be noted that the term “III-V compound semiconductor material”is used throughout this application to include a semiconductor materialthat includes at least one element or a mixture of elements from GroupIIIA of the Periodic Table of Elements and at least one element or amixture of elements from Group VA of the Periodic Table of Elements. TheIII-V compound semiconductor material may be a single layered materialor a multilayered material including different III-V compoundsemiconductors stacked upon each other can be used. In the multilayeredembodiment, an upper layer of a III-V compound semiconductor is locatedon a lower layer of a different III-V compound material, wherein theupper layer has a wider-band gap than that of the lower layer, is used.A III-V layer may also be grown on a IVA elemental semiconductor, e.g.,GaP on Si or GaA on Ge or vice a versa.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1D are pictorial representations (through cross sectionalviews) depicting one embodiment of the present invention.

FIGS. 2A-E are pictorial representations (through cross sectional views)depicting another embodiment of the present invention.

FIG. 3 is a pictorial representation (through a cross sectional view)depicting a FET that includes the inventive semiconductor structure.

FIG. 4A is a graph showing the C-V characteristics of a MOS capacitorcomprising GaAs/amorphous Si/SiO_(x)/HfO₂, after annealing at 700° C.for 1 minute in a nitrogen ambient.

FIG. 4B is graph showing the interface state density as a function ofgate voltage of the MOS capacitor mentioned in FIG. 4A.

DETAILED DESCRIPTION OF THE INVENTION

The present invention, which provides a high k gate stack on a III-Vcompound semiconductor material as well as a method of fabricating thesame, will now be described in greater detail by referring to thefollowing discussion and drawings that accompany the presentapplication. It is noted that the drawings of the present applicationare provided for illustrative proposes and, as such, they are not drawnto scale.

Reference is first made to FIGS. 1A-1D, which are pictorialrepresentations (through cross sectional views) depicting one embodimentof the present invention. In this particular embodiment, asemiconducting layer 14 is first formed on a treated surface 11 of aIII-V compound semiconductor material 10 and thereafter a dielectricmaterial 16 having a dielectric constant of greater than that of silicondioxide is formed on the semiconducting layer 14.

Reference is first made to FIG. 1A which illustrates an initial III-Vcompound semiconductor material 10 that can be used in the presentinvention. As shown, the initial III-V compound semiconductor material10 has region 12 that includes native oxides, atomic Ga or As speciesand other contaminants such as, for example, C-containing compoundstherein. In accordance with the present invention, the initial III-Vcompound semiconductor material 10 used is a semiconductor material thatincludes at least one element or a mixture of elements from Group IIIAof the Periodic Table of Elements and at least one element or a mixtureof elements from Group VA of the Periodic Table of Elements.Illustrative examples of III-V compound semiconductors that can be usedas material 10 include, but are not limited to: GaAs, InP, InAs, GaP,InSb, GaSb, GaN, InGaAs, and InAsSb. Preferably the III-V compoundsemiconductor is one of GaAs optionally including In, or one of InSboptionally including As.

The III-V compound semiconductor material 10 may be a single layeredmaterial (as shown) or a multilayered material (see FIG. 2A, forexample) including different III-V compound semiconductors stacked uponeach other. In the multilayered embodiment, an upper layer of a III-Vcompound semiconductor is located on a lower layer of a different III-Vcompound material, wherein the upper layer has a wider-band gap than thelower layer. Some examples of such materials include, but are notlimited to: an AlGaAs layer atop a InGaAs layer, a InGaP layer locatedatop a InGaAs layer, InAlAs layer atop a InGaAs layer, or a AlSb layeratop an InAsSb layer. A III-V layer may also be grown on a IVA elementalsemiconductor, e.g., GaP on Si or GaA on Ge or vice a versa.

The region 12 of native oxides and other contaminates typically includesat least an oxide of one of the elements of the initial III-V compoundsemiconductor material. For example, if the initial III-V compoundsemiconductor material 10 is GaAs, region 12 would include an oxide ofGa and/or an oxide of As. The initial III-V compound semiconductormaterial 10 includes an untreated surface at this point of the presentinvention which, if used without cleaning and passivated, would resultin a structure that is pinned and has a high interface state density (onthe order of about 10¹³ cm⁻² eV⁻¹ or greater).

FIG. 1B shows the III-V compound semiconductor material 10 of FIG. 1Aafter the region 12 of native oxides and other contaminates is removedfrom the material forming a treated surface 11. The treated surface 11which contains essentially no oxides and other contaminates is formed byutilizing a desorption process or by utilizing a H plasma precleaningprocess. By “essentially free of oxide” it is meant that the oxidecontent is about 10⁻² of a monolayer or less.

When a desorption process is used to remove region 12 forming thetreated surface 11, the desorption is carried out in vacuum or an inertambient such as, for example, N₂, He, Ar or a mixture thereof, at atemperature of about 600° C. or greater. The desorption is typicallyperformed in the presence of a partial pressure of As wherein a partialpressure equivalent to an incident flux of about 10¹⁴ As molecules cm⁻²or higher is established.

Although desorption can be used, it is preferred in the presentinvention that the region 12 is removed from the III-V compoundsemiconductor material 10 utilizing a H plasma process. The H plasmaprocess includes providing a plasma of hydrogen, H, using a hydrogensource such as, for example, molecular or, more preferably, atomichydrogen. The hydrogen plasma is a neutral, highly ionized hydrogen gasthat consisting of neutral atoms or molecules, positive ions and freeelectrons. Ionization of the hydrogen source is typically carried out ina reactor chamber in which the ionization process is achieved bysubjecting the source to strong DC or AC electromagnetic fields.Alternatively, the ionization of the hydrogen source is performed bybombarding the gate atoms with an appropriate electron source.

In accordance with a preferred embodiment of the present invention, thehydrogen plasma process used to provide the treated surface 11 isperformed at a temperature of about 300° C. or less.

As stated above, this step of the present invention removes the region12 including at least the native oxides of the III-V compoundsemiconductor material from the initial material providing a treatedsurface 11 such as shown, for example, in FIG. 1B. The interface formedat the treated surface located between the III-V compound semiconductor10 and the semiconductor layer (to be subsequently formed) has a lowinterface state density of on the order of about 10¹² cm⁻² eV⁻¹ or less.

The thickness of the treated surface 11 may vary depending on thetechnique used in forming the same and the exact conditions employed.Typically, the treated surface 11 has a thickness that is about a fewmonolayers or greater.

After forming the treated surface 11, a semiconducting layer 14 isformed thereon providing the structure shown, for example, in FIG. 1C.The semiconducting layer 14 may be crystalline or, more preferably,amorphous. The term “semiconducting layer” denotes a layer including Si,Ge alloys, SiGe, SiC, SiGeC and the like. Preferably, the semiconductinglayer 14 is comprised of Si. In accordance with the present invention,the semiconducting layer 14 is formed in-situ in the same reactorchamber as used in providing the treated surface 11. This step providesa semiconducting layer that passivates the previously cleaned III-Vcompound semiconductor material. The semiconducting layer 14 is formedby molecular beam epitaxy (MBE), chemical vapor deposition (CD), andother like deposition processes. Preferably, MBE is used in forming thesemiconducting layer 14.

The thickness of the semiconducting layer 14 may vary depending on thetechnique used in forming the same. Typically, the semiconducting layer14 has a thickness from about 0.5 to about 5 nm, with a thickness fromabout 0.5 to about 2 nm being even more typical.

In the specific embodiment illustrated, a dielectric material 16 havinga dielectric constant of greater than that of silicon dioxide is formedon the surface of the semiconducting layer 14. The dielectric material16 employed in the present invention comprises any metal oxide or mixedmetal oxide that is typically used as a gate dielectric or a capacitordielectric in semiconductor device manufacturing. Examples of suchdielectric materials (which can be referred to as a high k dielectricsince they have a dielectric constant of that which is greater thansilicon dioxide) include, but are not limited to: Al₂O₃, AlON, Ta₂O₅,TiO₂, La₂O₃, SrTiO₃, LaAlO₃, ZrO₂, Y₂O₃, Gd₂O₃, MgO, MgNO, Hf-baseddiele described in greater detail herein below), and combinationsincluding multilayers thereof.

The term ‘Hf-based dielectric’ is intended herein to include any high kdielectric containing hafiium, Hf. Examples of such Hf-based dielectricscomprise hafnium oxide (HfO₂), hafiiium silicate (HfSiO_(x)), Hf siliconoxynitride (HfSiON), HfLaO_(x), HfLaSiO_(x), HfLaSiON_(x), ormultilayers thereof. Typically, the Hf-based dielectric is hafnium oxideor hafnium silicate. Hf-based dielectrics typically have a dielectricconstant that is greater than about 10.0.

The physical thickness of the dielectric material 16 may vary, buttypically, the dielectric material 16 has a thickness from about 0.2 toabout 20 nm, with a thickness from about 0.5 to about 10 nm being moretypical. The dielectric material 16 may be formed in-situ or ex-situutilizing any conventional deposition process including, for example,chemical vapor deposition, PECVD, atomic layer deposition, chemicalsolution deposition, MOCVD, evaporation and other like depositionprocesses.

In one embodiment of the present invention, the dielectric material 16is hafnium oxide that is formed by MOCVD were hafnium-tetrabutoxide (aHf-precursor) and O₂ are used. In such an embodiment, the O₂ may bemolecular oxygen, or preferably, atomic oxygen is used. The depositionof Hf oxide occurs using a chamber pressure of about 1 Torr or less anda substrate temperature of about 200° C. or greater. In anotherembodiment of the present invention, the dielectric material 16 ishafnium silicate which is formed by MOCVD using the precursorHf-tetrabutoxide, O₂, and SiH₄; (ii) a chamber pressure of about 1 Torror less; and (iii) a substrate temperature of about 200° C. or greatermay also be used.

Reference is now made to FIGS. 2A-2E which illustrates anotherembodiment of the present invention. In this embodiment of the presentinvention, a semiconducting layer 14 is first formed on a treatedsurface 11 of a III-V compound semiconductor material 10 (including topand bottom layers as described above) and thereafter the semiconductinglayer 14 is completely or partially converted into a layer 15 includingat least a surface region comprised of AO_(x)N_(y), wherein A is asemiconducting material, x is 0 to 1, y is 0 to 1 and x and y are bothnot zero. In the embodiment where complete conversion is achieved, layer15 is completely comprised of AO_(x)N_(y). In embodiments wherepartially conversion is achieved, the upper surface portion of layer 15is comprised of AO_(x)N_(y) and the remaining portion of layer 15 iscomprised of the semiconducting material. FIG. 3 shows such anembodiment, wherein 15A is the remaining semiconducting material oflayer 14 and 15B is the AO_(x)N_(y) material. Note that in FIG. 3, theremaining semiconducting layer is optional. In either embodiment, thetreated surface is passivated with either a AO_(x)N_(y) layer or amaterial stack comprising, from bottom to top, a semiconducting materialand a AO_(x)N_(y) layer.

This embodiment shown in FIGS. 2A-2E begins by first providing thestructure shown in FIG. 2A which includes a III-V compound semiconductormaterial 10 having a region 12 of native oxides and other contaminantstherein. The semiconductor material 10 and the region 12 are the same asdescribed above for FIG. 1A. It is noted that in these drawings, thesemiconductor material 10 is shown as including a top III-V compoundsemiconductor layer 10B that has a wider band gap than that of the lowerIII-V compound semiconductor layer 10A. FIG. 2B illustrates thestructure that is formed after removing the region 12 from the structureand forming the treated surface 11 therein. This step of the illustratedembodiment is the same as that described above for FIG. 1B. Next, and asis shown in FIG. 2C, a semiconducting layer 14 (as described above) isformed on the treated surface 11.

After forming the semiconducting layer 14, layer 14 is convertedcompletely or partially converted into a layer 15 that is comprised ofat least a surface region including AO_(x)N_(y) wherein A is asemiconducting material, x is 0 to 1, y is 0 to 1 and x and y are bothnot zero. The resultant structure including layer 15 is shown, forexample, in FIG. 2D. In accordance with this embodiment of the presentinvention, the semiconducting layer 14 is subjected to a nitridation,oxidation or oxynitridation process which may be performed in-situ orex-situ utilizing conventional conditions that are well known in theart. Plasma and thermal techniques are both contemplated herein. In thecase of semiconducting layer 14 being Si, a SiN_(y) layer can be formedby exposing the semiconducting layer 14 to atomic nitrogen, with apartial pressure typically in the range of 10⁻⁶ to 10⁻⁴ Torr, at atemperature in the range of about 200° C. or greater, and a SiO_(x)layer to atomic O, with a partial pressure typically in the range of10⁻⁶ to 10⁻⁴ Torr at a temperature in the range of about 200° C. orgreater, and a SiO_(x)N_(y) layer can be formed by utilizing asequential or concurrent combination of these conditions. It is notedthat other conditions can be used besides those mentioned herein forthis step of the present invention. In accordance with the presentinvention, it is preferred that this step of the present invention byperformed in-situ. The conditions and duration of the converting willdetermine whether the semiconducting layer 14 is completely (typicallycharacterized by longer processing times) or partially modified(typically characterized by shorter processing times).

When complete conversion is achieved, the semiconducting layer 14 ismodified to a AO_(x)N_(y) layer, wherein A, x and y are as definedabove. When partial conversion is achieved, an upper surface region ofthe originally formed semiconducting layer 14 is modified to include aAO_(x)N_(y) surface layer that is located above the remainingsemiconducting material. In this particular embodiment, the dielectricmaterial is formed on the converted upper surface region. In such anembodiment, the upper surface region including the AO_(x)N_(y) surfacelayer has a thickness from about 0.5 to about 8 nm, with a thickness ofabout 0.5 to about 2 nm being even more typical.

FIG. 2E illustrates the structure after a dielectric material 16 (asdescribed above) is formed on layer 15. Notwithstanding partial orcomplete conversion of layer 15, the dielectric material 16 is formed ona surface that is comprised of AO_(x)N_(y).

The material stacks shown in FIG. 1D or 2E can be used in fabricating ametal oxide semiconductor capacitor (MOSCAP) and/or a MOSFET utilizingconventional processes that are well known in the art. One example of aMOSFET is shown in FIG. 3; in this drawing reference numeral 10 denotesthe III-V compound semiconductor, reference numeral 11 denotes thetreated surface, reference numeral 15B denotes the AO_(x)N_(y) layer,reference numeral 15A denotes the remaining semiconducting material ofthe semiconducting layer; reference numeral 16 denotes the high kdielectric material, reference numeral 18 denotes the gate electrode,and reference numeral 20 denotes the source/drain diffusion regions. Ineach case, an electrode or an electrode stack is formed on the materialstacks shown in FIG. 1D or 2E and thereafter these materials layers arepatterned by lithography and etching.

The electrode or electrode stack, which comprises at least oneconductive material, is formed utilizing a known deposition process suchas, for example, physical vapor deposition, CVD or evaporation. Theconductive material used as the electrode includes, but is not limitedto: Si-containing materials such as Si or a SiGe alloy layer in eithersingle crystal, polycrystalline or amorphous form. The conductivematerial may also be a conductive metal or a conductive metal alloy.Combinations of the aforementioned conductive materials are alsocontemplated herein. Si-containing materials are preferred, with polySibeing most preferred. In addition to aforementioned conductivematerials, the present invention also contemplates instances wherein theconductor is fully silicided or a stack including a combination of asilicide and Si or SiGe. The silicide is made using a conventionalsilicidation process well known to those skilled in the art. Fullysilicided layers can be formed using a conventional replacement gateprocess; the details of which are not critical to the practice of thepresent invention. The blanket layer of conductive material may be dopedor undoped. If doped, an in-situ doping deposition process may beemployed in forming the same. Alternatively, a doped conductive materialcan be formed by deposition, ion implantation and annealing. The ionimplantation and annealing can occur prior to or after a subsequentetching step that patterns the material stack. The doping of theconductive material will shift the workfunction of the electrode formed.The thickness, i.e., height, of the electrode deposited at this point ofthe present invention may vary depending on the deposition processemployed. Typically, the electrode has a vertical thickness from about20 to about 180 nm, with a thickness from about 40 to about 150 nm beingmore typical.

The MOSCAP formation typically includes forming a thermal, chemical ordeposited sacrificial oxide (not shown) on the surface of the III-Vcompound semiconductor material. Using lithography, the active areas ofthe capacitor structure are opened in the field oxide by etching.Following the removal of the oxide, the material stack as shown in FIG.1D or 2E is formed as described above. Specifically, the material stackis provided, patterned by lithography and etching, and then a gateelectrode including dopants is formed on the dielectric stack. In thecase of a poly-silicon gate electrode, the dopants are typically P orAs, and can be incorporated by implantation with a typical dose in therange of 1×10¹⁵ ions/cm² to 5×10¹⁵ ions/cm², or in situ doping duringpoly-silicon deposition using dopant precursor species such as AsH₃ orPH₃. The dopants are activated using an activation anneal that isperformed at 900° C. to 1000° C. for about 5 seconds. The MOS cap couldalso incorporate a metal or metal-alloy stack alone or in combinationwith a polysilicon gate electrode. In some cases, an anneal step can beperformed before or after the deposition of the gate electrode. Saidanneal step is typically performed between 500° to 800° C., and istypically performed in a nitrogen ambient.

The MOSFET formation includes first forming isolation regions, such astrench isolation regions, within the III-V compound semiconductormaterial described above. A sacrificial oxide layer can be formed atopthe III-V compound semiconductor material to form the isolation regions.Similar to the MOSCAP and after removing the sacrificial oxide, amaterial stack as described above is formed. Next, a gate electrode isformed and the material stack is then patterned. Following patterning ofthe material stack, at least one spacer is typically, but not always,formed on exposed sidewalls of each patterned material stack. The atleast one spacer is comprised of an insulator such as an oxide, nitride,oxynitride and/or any combination thereof. The at least one spacer isformed by deposition and etching.

The width of the at least one spacer must be sufficiently wide such thatthe source and drain silicide contacts (to be subsequently formed) donot encroach underneath the edges of the patterned material stack.Typically, the source/drain silicide does not encroach underneath theedges of the patterned material stack when the at least one spacer has awidth, as measured at the bottom, from about 20 to about 80 nm.

The patterned material stack can also be passivated at this point of thepresent invention by subjecting the same to a thermal oxidation,nitridation or oxynitridation process. The passivation step forms a thinlayer of passivating material about the material stack. This step may beused instead or in conjunction with the previous step of spacerformation. When used with the spacer formation step, spacer formationoccurs after the material stack passivation process.

Source/drain diffusion regions are then formed into the substrate. Thesource/drain diffusion regions are formed utilizing ion implantation andan annealing step. Typically, a raised source/drain process is used. Theannealing step serves to activate the dopants that were implanted by theprevious implant step. The conditions for the ion implantation andannealing are well known to those skilled in the art. The source/draindiffusion regions may also include extension implant regions which areformed prior to source/drain implantation using a conventional extensionimplant. The extension implant may be followed by an activation anneal,or alternatively the dopants implanted during the extension implant andthe source/drain implant can be activated using the same activationanneal cycle. Halo implants are also contemplated herein.

In some cases, an annealing step as described above can be performed.Further CMOS processing such as formation of silicided contacts(source/drain and gate) as well as formation of BEOL(back-end-of-the-line) interconnect levels with metal interconnects canbe formed utilizing processing steps that are well known to thoseskilled in the art.

The following example is provided for illustrative purposes and thus itshould not be construed to limit the scope of the present application inany way.

EXAMPLE

In this example, a MOSCAP was prepared utilizing a semiconductorstructure in accordance with the present invention. The inventivestructure included, from bottom to top, an atomic-H passivated GaAssubstrate, an amorphous Si layer, SiO_(x) and HfO₂. The structure wasformed utilizing the inventive processing details described above. Afterformation, a gate electrode was formed thereon and the structure wasannealed at 700° C., 1 min., in nitrogen.

FIG. 4A shows the CV curves of such a MOSCAP at 1 kHz, 10 kHz, 100 kHzand 1 MHz. Specifically, the CV curves have very low frequencydispersion, which is indicative of low interface state density. FIG. 4Bshows the D_(it) extracted as a function of gate voltage of the sameMOSCAP as in FIG. 4A using the frequency-dependent method well known inthe art. The results show a minimum D_(it) value of 6×10¹¹ cm⁻²/eV,which is over an order of magnitude lower than typically obtained onMOSCAPs with HfO₂ directly on an unpassivated GaAs.

While the present invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

1. A method of forming a material stack on a III-V compoundsemiconductor comprising: removing native oxides from a III-V compoundsemiconductor material to provide a treated surface; forming asemiconducting layer in-situ on said treated surface of said III-Vcompound semiconductor material; and forming a dielectric materialhaving a dielectric constant that is greater than silicon dioxide onsaid semiconducting layer.
 2. The method of claim 1 wherein saidremoving said native oxides comprises desorption at a temperature ofabout 600° C. or greater.
 3. The method of claim 1 wherein said removingsaid native oxides comprises a plasma H process.
 4. The method of claim1 wherein said semiconducting layer is formed by epitaxy.
 5. The methodof claim 1 further comprising completely or partially converting thesemiconducting layer into a AO_(x)N_(y) layer, wherein A is asemiconducting material, x is 0 to 1, y is 0 to 1 and x and y are bothnot zero, prior to forming the dielectric material.
 6. The method ofclaim 1 wherein each of said steps is performed in-situ.
 7. The methodof claim 1 wherein each of said steps is performed at a temperature ofless than 300° C.
 8. A method of forming a material stack on a III-Vcompound semiconductor comprising: removing native oxides from a III-Vcompound semiconductor material to provide a treated surface; forming asemiconducting layer in-situ on said treated surface of said III-Vcompound semiconductor material; converting at least an upper surfaceregion of said semiconducting layer to a region comprised of AO_(x)N_(y)wherein A is a semiconducting material, x is from 0 to 1, y is from 0 to1 and x and y are both not zero; and forming a dielectric materialhaving a dielectric constant that is greater than silicon dioxide on theupper surface region of said semiconducting layer.
 9. The method ofclaim 8 wherein said removing said native oxides comprises desorption ata temperature of about 600° C. or greater.
 10. The method of claim 8wherein said removing said native oxides comprises a plasma H process.11. The method of claim 8 wherein said semiconducting layer formed byepitaxy.
 12. The method of claim 8 wherein each of said steps isperformed in-situ.
 13. The method of claim 8 wherein each of said stepsis performed at a temperature of less than 300° C.
 14. A semiconductorstructure comprising: a III-V compound semiconductor material having asurface that is essentially free of oxides; a semiconducting layerlocated on said surface, wherein an interface is present between theIII-V compound semiconductor material and the semiconducting layer thathas an interface state density of about 10¹² cm⁻² eV⁻¹ or less; and adielectric material having dielectric constant greater than that ofsilicon dioxide located on said semiconducting layer.
 15. Thesemiconductor structure of claim 14 wherein said III-V compoundsemiconductor material includes an upper layer and a lower layer,wherein said upper layer has a wider-band gap than said lower layer. 16.The semiconductor structure of claim 14 wherein said semiconductinglayer is amorphous.
 17. The semiconductor structure of claim 14 whereinsaid semiconducting layer is Si.
 18. The semiconductor structure ofclaim 14 wherein said semiconducting layer includes at least a surfaceregion of AO_(x)N_(y) wherein A is a semiconducting material, x is from0 to 1, y is from 0 to 1, both x and y are not zero and said dielectricmaterial is located on said surface region of AO_(x)N_(y).
 19. Thesemiconductor structure of claim 14 wherein said semiconducting layer isreplaced completely by an AO_(x)N_(y) layer wherein A is asemiconducting material, x is from 0 to 1 and y is from 0 to 1 and saiddielectric material is located on said AO_(x)N_(y) layer.
 20. Thesemiconductor structure of claim 14 wherein said dielectric material isa Hf-based dielectric.
 21. The semiconductor structure of claim 14further comprising an electrode or electrode stack on said dielectricmaterial.
 22. The semiconductor structure of claim 14 wherein saiddielectric material is a gate dielectric of at least one field effecttransistor device.
 23. A method of enhancing the activation of implanteddopants within a III/V compound semiconductor material comprising:providing a semiconducting cap layer atop a III/V compound semiconductorthat has a surface that is essentially free of oxides, said III/Vcompound semiconductor including n-type dopants, p-type dopants or both;and annealing the dopants to provide at least one activated dopantregion in said III/V compound semiconductor.